EDN

Building an FPGA FIFO without using logic resources

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...
EDN

An interesting Gray code FIFO counter question

Do you recall the “How To” article I posted on Gray Codes a while back. Well, a reader has just emailed me with an interesting question. I'm up to my ears in alligators as usual (work-wise) and ...
Design-Reuse

Clock domain modeling is essential in high density SoC design

Whether designing SOCs with traditional synchronous logic or alternative locally, or self-clocked "asynchronous" blocks, verification has become more important, difficult and time consuming, ...